IP Cores - logiI2S

オーディオ I2S トランスミッター/レシーバ

Key Features

  • Highly configurable:
  • - Timing generator only
    - Controller + I2S RX
    - Controller + I2S TX
    - Controller + I2S TX + I2S RX
    - I2S TX only
    - I2S RX only
    - I2S TX + I2S RX only

  • I2S compatible controller
  • CoreConnectTM OPB compatible registers' interface
  • CoreConnect PLB compatible memory interface
  • Adjustable audio sample widths: 8, 16, 18, 20 or 24 bits
  • Adjustable memory buffers for storing/reading samples to/from the memory
  • Fully embedded into Xilinx® XPS and the EDK

Description

The logiI2S is Xylon logicBRICKSTM IP core compatible with the I2S electrical serial bus interface standard used for connecting digital audio devices. This IP core enables an easy interconnection of external audio devices to the Xilinx FPGA that can generate or transform the digital audio data. The logiI2S IP core is fully embedded into Xilinx Platform Studio and the EDK, and can be easily customized and tuned for optimal slice consumption and features set. This IP core allows for an easy audio integration into Xilinx FPGA based embedded systems.
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