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UART( Universal Asynchronous Receiver/Transmitter )
Key Features
- Baud rates from 5 bps to 3 Mbps
- Programmable data length (5, 6, 7, or 8 bits)
- Programmable number of stop bits (1, 1.5, 2)
- Programmable parity: none, even, odd, space and mark
- 128-byte deep TX and RX FIFO with readable levels and water level marks
- Detects framing error, parity error and 'break' error
- Automated flow control using CTS and RTS control signals
- Modem control functions (CTS, RTS, DSR, DTR, RI and DCD)
- Register interface either PLB or OPB compatible
- Fully embedded into XilinxR XPS and the EDK
Description
The logiUART is the logicBRICKS single-channel programmable UART designed for the Xilinx FPGAs. It offers simplicity in use and high overall performances. Communication speeds are supported in a wide range, starting from a few bps up to 3 Mbps. Available separated 128-bytes deep TX and RX FIFOs reduce the CPU overhead. Readable FIFO's pointers with supported interrupts allow flexible software control. Various character formats are supported. Different types of parity protection and framing errors are automatically supported too. The logiUART's registers interface can be configured for compatibility with either PLB or OPB bus through the Xilinx EDK GUI interface. It enables an easy integration into Xilinx FPGAs.
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