SDRAM メモリコントローラ/アビター
The logiMEM_arb Memory Controller and Arbiter IP core is specially designed for Xilinx® Spartan®-6 FPGA memory interfaces. This IP core supports up to 16 IP ports, up to 8 simultaneous IP memory accesses and different on-chip bus standards: AMBA® AXI4, CoreConnect PLB, Xilinx Cache Link, Xilinx Native Port Interface and Xylon Memory Bus (XMB)